1. Field of the Invention
The present invention relates to telecommunications systems and, in particular, to a digital controlled clock that utilizes a multi-phase ring oscillator to provide extremely fine resolution on the clock stepping utilized for recovering data from a received signal.
2. Discussion of the Prior Art
To reliably recover data from a received signal in some transmission systems, such as in Integrated Services Digital Network (ISDN) U-interface applications, there must be very stringent jitter control on the clock utilized for sampling the received signal. "Jitter" is a term used to describe short term variations of a digital signal from its ideal position in time.
It has been common in the past to use an analog phase locked loop for recovering sampling clocks from a received signal. However, analog phase locked loops are not easily integratable due to their large RC requirements for obtaining the necessary loop time constant. Therefore, extreme care must be taken in the fabrication of these integrated circuits to ensure consistent performance.
Digital phase locked loops that utilize a single phase clock do not provide fine enough resolution, resulting in unacceptably high jitter in the recovered sampling clock in some applications.
Digital phase locked loops that utilize multiphase clocks are also typically difficult to integrate due to the high speed and complexity of the conventional phase commutator circuitry required to switch among the multiple phases. Furthermore, proportional control is crude in these loops because only a single bit is controlling the phase advance/retard mechanism.
U S. Pat. No. 4,584,695, issued Apr. 22, 1986 to Wong et al, discloses a digital phase locked loop decoder that generates a sampling clock having both an effective sampling interval and clock stepping resolution that is shorter than the driver clock period. The Wong et al sampling clock generator relies on a three-stage oscillator that provides three clock signals having an equally-spaced phase relationship. A phase commutator responds to an advance/retard input to select one of the three phase clocks as the driver clock for the received signal sampler.
More specifically, each of the three stages of the Wong et al clock generator consists of an invertor and a series-connected amplifier. Thus, the period of each of the three phase outputs of the oscillator is six stage delays. Given this configuration, any phase output of the oscillator is paralleled by a phase step one-third of a period later in a second phase and a phase step one-third of a period earlier in the remaining phase. Each of the three phase output pulse trains is buffered by an amplifier and then reshaped by a set-reset flip-flop. The outputs of the three flip-flops are provided to commutator circuitry which makes corrections to the drive clock by selecting a leading or lagging phase to replace the current phase used as the driver clock signal. The commutator phase selection is implemented by providing each of the three oscillator phase outputs to a corresponding D-type flip-flop. A phase decoder provides an advance/retard signal to multiplexing circuitry indicating whether the driver clock signal is leading or lagging the data clock signal of incoming Manchester encoded data. The multiplexing circuitry drives the D flip-flops, the outputs of which are then processed by NOR gate logic to provide either an advanced or a retarded driver clock signal.
Although the sampling clock generator disclosed in the above-identified Wong et al patent represents a significant improvement over the prior art and is useful in a wide variety of applications, because of the limited number of stages utilized in the multiphase clock generator, it does not provide the degree of resolution required for data recovery in ISDN applications. Furthermore, the synchronous commutator technique utilized by Wong et al, if expanded to provide more clock phase stages and, thus, finer resolution, would require an inordinate and costly number of components to implement the required flip-flop/multiplexor scheme.
Therefore, it would be desirable to have available a simple, inexpensive sampling clock generator that provides high resolution phase stepping.